Taiwan is a global leader in high-tech manufacturing and semiconductor industries, but it has also become a target of cyberattacks. Security protection for smart manufacturing has become an issue that cannot be ignored. This project conducts forward-looking academic research and technology development on information security issues related to smart manufacturing. First, Sub-Project 3 develops a comprehensive, multi-layered security defense framework for smart manufacturing environments, which is achieved by integrating Zero Trust Architecture (ZTA) with AI-native security technologies. In the two years, we will gradually promote the construction of key components, including decentralized identity (DID)-based authentication mechanisms, AI-driven intrusion detection and behavior modeling, anti-poisoning mechanisms, and an integrated industrial security data lake. Secondly, Sub-Projects 4 and 5 propose technologies to ensure the cyber security of smart manufacturing supply chains from different perspectives. Sub-Project 4 constructs a cybersecurity protection framework for industrial control systems (ICS) by integrating dual-layer anomaly detection and horizontal federated learning, thereby enhancing the security resilience of Operational Technology (OT) environments. Sub-project 5 designs and implements an integrated intelligent Security Operations Center (SOC)for Operational Technology (OT) systems in critical infrastructure, addressing specific cybersecurity threat scenarios. The proposed system integrates Intrusion Detection Systems (IDS) and Endpoint Detection and Response (EDR) to enhance detection, alerting, and response capabilities. Expected outcomes include a feasible detection system for industrial fields, providing cybersecurity solutions that can be implemented in the critical infrastructure industry. Sub-projects 1 and 2 aim to improve the security of industrial control information hardware. Currently, designers use hardware description language (HDL) descriptions to define hardware architectures. However, if the HDL source code is not written rigorously, it will lead to security vulnerabilities that may be exploited by malicious attackers to cause serious damage to the system. Most hardware weaknesses are caused by designers not fully considering security issues. As the complexity of system chip design continues to increase, the workload of designers to manually diagnose security vulnerabilities has become huge.

Traditional manual detection methods are time-consuming and prone to errors. Therefore, the development of an automated vulnerability detection tool in Sub- project 1 has become an urgent problem to be solved. In order to solve the above problems, this project plans to develop an automated hardware vulnerability detection framework based on large language models (LLM) and establish a hardware weakness database as a design guide for designers. Sub-project 2 is dedicated to building a hardware application platform with data security protection. It proposes a hardware-based encryption and authentication mechanism for data security threats that may occur during sensing, transmission and storage. It includes the development of a prototype system for the architecture, the implementation of multiple security modules including symmetric and asymmetric encryption and decryption, hashing, physical non-copyable functions, random number generation and error correction codes, and the combination of image sensing equipment to complete the encryption anddecryption of real-time image data.